============================================================== Guild: wafer.space Community Channel: ℹ️ - Information / general Topic: Welcome to [wafer.space](https://wafer.space/) - documentation at [wafer.space github](https://github.com/wafer-space) - buy at [buy.wafer.space](https://buy.wafer.space) - archives at [discord.wafer.space](https://discord.wafer.space/) After: 2025-04-30 11:59 p.m. Before: 2025-06-01 12:00 a.m. ============================================================== [2025-05-03 5:52 p.m.] mithro_ Hi everyone! The logo I've ended up going with is the following [2025-05-03 5:52 p.m.] mithro_ {Attachments} 2025-05_media/Wafer.Space.bw.128x128-F9BAE.png {Reactions} ✨ (4) 🚀 (3) ⛵ [2025-05-12 3:12 a.m.] mithro_ BTW I've started putting together a list of projects and stuff I'm thinking about putting in empty slots on the first shuttle run [2025-05-12 3:12 a.m.] mithro_ https://docs.google.com/document/d/1kyo9Qcsu0RMXwUS2woMCOvf14YvA0IqpgDkZmIRFZpc/edit?tab=t.0 {Embed} https://docs.google.com/document/d/1kyo9Qcsu0RMXwUS2woMCOvf14YvA0IqpgDkZmIRFZpc/edit?tab=t.0 wafer.space GF180MCU Projects wafer.space GF180MCU Projects 2025-05_media/AHkbwyJzt_CdjKoS94LsetZZh7Rab7FNnVZdpGAPlR-6FD21 {Reactions} 🚀 [2025-05-13 5:31 a.m.] algofoogle I’m trying to think of wacky ideas… maybe some sort of die that is actually a micro-probe array for testing other dice, flip-chip-bed-of-nails? I wonder if there’s any way you could make a “squishy” interposer to put between such a die and the thing you want to probe [2025-05-15 2:10 p.m.] mattvenn how are things going @Tim 'mithro' Ansell ? [2025-05-15 2:31 p.m.] mithro_ Slowly getting there with everything {Reactions} 👍 [2025-05-15 2:56 p.m.] mithro_ @Matt Venn - It's been fun to actually get closer to the metal then I have been for a while [2025-05-15 3:11 p.m.] mithro_ @Matt Venn - Figuring out what the limits are has been interesting, specially things like this table -> {Attachments} 2025-05_media/image-7BDE8.png [2025-05-15 4:00 p.m.] 246tnt What are you trying to compare with that table 🤔 [2025-05-15 4:01 p.m.] 246tnt It's the number of 3 input AND cells you can put in the same area as an SRAM ... But I'm not sure how that metric is helpful ? [2025-05-15 4:09 p.m.] mithro_ @tnt - Number of latches (IE 1 bit of storage) to SRAM [2025-05-15 4:10 p.m.] 246tnt Where did you find a latch in the gf180 standard cell library ? I didn't see one at first glance. [2025-05-15 4:10 p.m.] mithro_ @tnt - {Attachments} 2025-05_media/image-E6826.png [2025-05-15 4:11 p.m.] mithro_ https://docs.google.com/spreadsheets/d/1__CaMhJ88QpAhJFrScrBWYnRrFHs8kl6nTi9r7uFDIw/edit?gid=498165305#gid=498165305 {Embed} https://docs.google.com/spreadsheets/d/1__CaMhJ88QpAhJFrScrBWYnRrFHs8kl6nTi9r7uFDIw/edit?gid=498165305 GF180MCU Standard Sizing um sizing 2025-05_media/AHkbwyJ_P9R_ZrS41gkPSLiD6HvQxHYS2D1vuJlaEI-0EB86 [2025-05-15 4:11 p.m.] 246tnt Oh, I see, they don't have the same naming scheme. [2025-05-15 4:12 p.m.] 246tnt I was looking for `dlxxx` for latches but it's named `latq` [2025-05-15 4:12 p.m.] mithro_ {Attachments} 2025-05_media/image-CF2A4.png [2025-05-15 4:13 p.m.] mithro_ @tnt - Dammit, that was an oversight, seems like they should have been dlxxx [2025-05-15 4:13 p.m.] mithro_ @tnt - I was looking at how to do a compact standard cell based "programmable" mux [2025-05-15 4:13 p.m.] mithro_ https://docs.google.com/drawings/d/1YEM74jc4aNdtRJ-IsS7GyEP_q4M2Ckr523fqsclLHLc/edit {Embed} https://docs.google.com/drawings/d/1YEM74jc4aNdtRJ-IsS7GyEP_q4M2Ckr523fqsclLHLc/edit GF180MCU Programmable Mux Layout I2 I3 I1 I0 Z S1 S0 Latch A Latch B Latch D Latch C MUX4 Q I2 I3 Q Q Q I1 I0 Z S1 S0 D E D E D E D E Latch A Latch B Latch D Latch C MUX4 Q Q D E D E D Q D Q Q E E Programming Data Shift Register Path Programming Data Clock Path Programming Data to Mux Path Latch A BUFZ Latch A BUFZ Latch A BUFZ ... 2025-05_media/AHkbwyJm3oowToxfoXcAzXjmOt3iyMXm-I31sdBHzj-FDF05 [2025-05-15 4:14 p.m.] mithro_ ``` gf180mcu_fd_sc_mcu7t5v0__mux4_4 -- 21.28 um gf180mcu_fd_sc_mcu7t5v0__latq_1 -- 11.20 um ``` [2025-05-15 4:16 p.m.] mithro_ Then I discovered the `bufz_4` is also 11.20um in size [2025-05-15 4:17 p.m.] 246tnt Not sure what you mean exactly by "programmable mux" TBH. [2025-05-15 4:19 p.m.] mithro_ A mux where the input choice is controlled by a storage element [2025-05-15 4:19 p.m.] 246tnt Ok. So like a FPGA LUT cell basically. [2025-05-15 4:20 p.m.] 246tnt But your diagram seem to show a serial configuraiton like a shift register ... and you can only do that with actul register (i.e. FFs), you can't make a shift register with latches, that just doesn't work. [2025-05-15 4:20 p.m.] mithro_ Oh, yeah - I guess you are right [2025-05-15 4:25 p.m.] mithro_ @tnt - Actually, if you had two enables then it should work, right? [2025-05-15 4:26 p.m.] 246tnt No. Two consecutive latches will always have the same output. [2025-05-15 4:26 p.m.] 246tnt Basically two latches with non overlapping enable is one flip-flop ... [2025-05-15 4:32 p.m.] mithro_ @tnt - If you have Enable A and Enable B, then every "even numbered latch" in the chain is connected to Enable A and ever "old numbered" latch in the chain is connected to Enable B, then you should be able to pulse Enable A, then Enable B, right? [2025-05-15 4:35 p.m.] 246tnt Say you pulse Enable A ... all `A` latches now hold the value of the `B` latches before them. Whatever value they used to hold is now gone. So you only have N/2 distinct values in the chain. [2025-05-15 4:39 p.m.] mithro_ Ahh, yeah [2025-05-15 4:40 p.m.] mithro_ Having the alternative enables does prevent hold violations between the elements if they where flipflops [2025-05-15 4:43 p.m.] mithro_ What is it that the AI's always say when you point out that there stuff is borked? 😛 [2025-05-15 4:50 p.m.] mithro_ ``` 2 * gf180mcu_fd_sc_mcu7t5v0__dffq_1 ~= 1 * gf180mcu_fd_sc_mcu7t5v0__mux4_1 + 1 * gf180mcu_fd_sc_mcu7t5v0__inv_8 ``` [2025-05-15 4:54 p.m.] mithro_ I also have yet to understand if the routing I'm drawing is even possible on the technology [2025-05-15 4:58 p.m.] mithro_ Sadly the numbers don't line up as well.... [2025-05-15 5:01 p.m.] mithro_ Stupid reality screwing up nice theory 🙂 [2025-05-15 5:11 p.m.] mithro_ {Attachments} 2025-05_media/image-3D558.png [2025-05-15 5:26 p.m.] mithro_ I wonder how the drive strength effects timing and stuff [2025-05-15 5:31 p.m.] mithro_ I assume that a higher drive strength cell also puts more load on the cell driving it? [2025-05-15 5:32 p.m.] mithro_ @tnt - I do have your talk with Matt Venn on the Tiny Tapeout multiplexer stuff on my to watch list [2025-05-15 6:02 p.m.] 246tnt Usually large size buffer like _8 / _12 / _16 will have a progressive build up internally. Like the first stage will be a single transitor inverter, then driving a 4 transistor one then drivingthe final 16 one for instance. [2025-05-15 6:12 p.m.] 246tnt And 2 clock for FFs is a horrible idea. It doesn't help for hold violations, on the contrary, it's a sure way to have more issues ... [2025-05-15 11:16 p.m.] mithro_ @tnt - I found these diagrams from a long while back. I think it actually connected back to the N/2 distinct values on the chain issue you pointed out with the latches -- Tim Edwards explained something about how flip flops are kinda of built internally with two latches with one enable driven by an inverted clock signal so both latches are never "open/passing data" at the same time. Somehow I've forgotten all the correct details and am super fuzzy on what I'm trying to say here. {Attachments} 2025-05_media/image-C538E.png 2025-05_media/image-412E2.png [2025-05-16 1:19 a.m.] mithro_ Ahh ha {Attachments} 2025-05_media/7a022f70-9594-4233-8ff0-a80683b59b9b-82087.png [2025-05-16 7:44 a.m.] 246tnt Yes, if you construct the FFs "manually" using 2 latches, then using two non-overlapping clocks you can make things safer ... assuming you generate those two non overlapping clocks correcly. [2025-05-16 8:00 a.m.] mattvenn I'm missing how this relates to an mpw service, can someone explain? [2025-05-16 9:30 a.m.] 246tnt 🤷 [2025-05-16 11:55 a.m.] mattvenn 😅 [2025-05-17 5:51 p.m.] mithro_ @Matt Venn - The discussion started at "Figuring out what the limits are has been interesting" {Reactions} 👍 [2025-05-17 5:54 p.m.] mithro_ @Matt Venn - All comes back to trying to make sure that I can run the MPW even if not fully full. {Reactions} 👍 [2025-05-20 4:30 p.m.] carlfk what does "not full" mean? [2025-05-20 4:30 p.m.] mattvenn as in if only 50% of the project slots are sold [2025-05-20 4:32 p.m.] carlfk other than money, what would prevent doing a run? [2025-05-20 4:33 p.m.] carlfk does more mask detail cost more? [2025-05-20 4:35 p.m.] carlfk I would expect blank slots could be filled in with something, like lets make a bunch of similar tests to see how well they line up with simulations [2025-05-20 4:38 p.m.] mattvenn If it were me, just the money. How long can I go before I'm broke [2025-05-20 4:39 p.m.] mattvenn And yes blank slots can be filled, but high quality projects are rare and take a lot of work [2025-05-20 4:42 p.m.] carlfk k - that all fits with what I figured. [2025-05-20 4:42 p.m.] carlfk sounds like we should have a bunch of filler projects so the space doesn't go to waste [2025-05-20 8:56 p.m.] algofoogle Totally… get cracking! https://discord.com/channels/1361349522684510449/1361349523724570941/1371324214178611271 [2025-05-26 2:35 a.m.] mithro_ That is what https://docs.google.com/document/d/1kyo9Qcsu0RMXwUS2woMCOvf14YvA0IqpgDkZmIRFZpc/edit?tab=t.0 is all about {Embed} https://docs.google.com/document/d/1kyo9Qcsu0RMXwUS2woMCOvf14YvA0IqpgDkZmIRFZpc/edit?tab=t.0 wafer.space GF180MCU Projects wafer.space GF180MCU Projects Single Usage Tiles Programmable Tiles One Time Programmable 2025-05_media/AHkbwyLSQFHCS919akN0IpqXAAh_tM5wJFTcoUhOPY-90B47 [2025-05-26 3:37 p.m.] carlfk how about: power rail popper. a set of decreasing width traces? to see how much power they can really handle compared to what the simulator says {Reactions} 👍 [2025-05-27 4:09 a.m.] algofoogle I always wanted to try a project like that… a way to test all the things that could go wrong. DRC violations (so long as they don’t violate MR), wrong voltages going to a bunch of devices, chips that could self-destruct (charge pumps?), ESD-unprotected stuff… what else? [2025-05-29 1:08 a.m.] mithro_ @algofoogle (Anton Maurovic) - https://github.com/egorxe/gf180_efuse_compiler {Embed} https://github.com/egorxe/gf180_efuse_compiler GitHub - egorxe/gf180_efuse_compiler: eFuse memory compiler for GF1... eFuse memory compiler for GF180MCU. Contribute to egorxe/gf180_efuse_compiler development by creating an account on GitHub. 2025-05_media/gf180_efuse_compiler-23014 [2025-05-29 1:45 a.m.] algofoogle Oh that’s interesting. Thanks Tim 🙂 I wonder how reliable the array was on GFMPW0/1. Efabless was always worried about how to produce a safe/reliable eFuse solution for Sky130. I remember fears about things either not popping, or doing so too violently (rupturing laminations or leading to shorts elsewhere) [2025-05-29 1:46 a.m.] mithro_ I'm sending an email to enquire about the status [2025-05-29 1:46 a.m.] mithro_ I don't think it ended up being taped out because the efuses require an extra mask layer or something [2025-05-29 6:00 a.m.] proppy Looking good guys, keep up the fantastic work! [2025-05-29 6:00 a.m.] proppy https://tenor.com/view/cat-cat-meme-funnt-cat-black-cat-sleepy-cat-gif-16409614852005252877 {Embed} https://tenor.com/view/cat-cat-meme-funnt-cat-black-cat-sleepy-cat-gif-16409614852005252877 2025-05_media/cat-cat-meme-BEDA4.png [2025-05-29 9:49 p.m.] mithro_ From the developer of the Efuse Compiler: ``` Here is a history of this Efuse compiler: 1. Originally the compiler was made in haste for the GFMPW-0 run. My chip with a 9 kBit Efuse block was accepted by Efabless, but unfortunately there was no full chip LVS available in Efabless tapeout flow at the time. So I've missed a critical flaw in this chip - VDD & GND stripes in Efuse blocks were not connected to top level power stripes. The only missing thing were vias connecting stripes on Metal5 to stripes on Metal4. 2. After discovering the power issue I thought there would be no hope to verify the Efuse block in this chip so when the chips arrived I tested mostly other parts of the chip. Efuse was dead as expected, but Caravel and some of my digital test structures worked flawlessly with VDD in range from 3 to 8 Volts which amazed me. GF180MCU seems to be a really robust process :). 3. For the GFMPW-1 I've submitted a chip with fixed power connections problem and introduced several small improvements in Efuse macro, but my chip was not selected for the run. 4. As missing top metal vias was the only thing standing between my curiosity and testing Efuse on GFMPW-0 chips, I thought that maybe it's possible to create vias on finished chips somehow. Some time ago I've got a contact of guys from chip testing industry from a friend, and they agreed to create a couple of vias for me. 5. After chip decap and vias creation on two of Efuse subblocks these subblocks miraculously just worked. I had no single write (one time obviously) or read error on all efuse bytes that were powered during several days I've tested this chip. 6. As I thought that accessible GF180 runs would never happen again I kinda lost the motivation in improving the compiler, but now if there is such a possibility I would like to make it useful. ``` [2025-05-29 9:49 p.m.] mithro_ @digshadow [2025-05-29 9:56 p.m.] mithro_ @digshadow - Should I ask the guy to send us some spare parts for you to look at / play with? (BTW Feel to respond to this next week after your conference.) {Reactions} 👍 [2025-05-29 10:22 p.m.] digshadow Yes, I don't really want to think about this right now, but in general I'm up for a lab day next week if you want to image some things [2025-05-30 12:45 a.m.] algofoogle Very cool 🙂 thanks for following up [2025-05-31 2:09 a.m.] mithro_ I started documenting my understanding around the GF's 180nm process technologies @ https://bit.ly/ws-gf180 {Embed} https://bit.ly/ws-gf180 GlobalFoundries 180nm Technologies (GF180MCU, GF180ULL, GF180BCD, G... GlobalFoundries 180nm Technologies bit.ly/ws-gf180 GlobalFoundries offers a wide range of different 180nm based technologies. These 180nm technologies are very configurable and offer; Multiple options in the number of metal layers. Different thickness for the top metal layer. A large number of "... 2025-05_media/AHkbwyI50vAck6KoFlJnZO4jWyoaARcGy0BCrcZQ4i-0A279 ============================================================== Exported 79 message(s) ==============================================================